1. Field of the Invention
The present invention relates to semiconductor devices and a method for fabricating them and, more particularly, to a method for fabricating DRAM (Dynamic Random Access Memory) cell capacitors that can be used in high-density integrated circuits.
2. Description of the Related Art
As the cell density of DRAM devices increases, there is a continuous need to maintain a sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuous need to further reduce the cell area. In order to keep the capacitance of storage capacitors in DRAMs at an acceptable value, many methods have been studied and developed. One approach is to use a film with a high dielectric constant such as BST (barium strontium titanate) for the storage electrode in the capacitors instead of conventional NO (Nitride Oxide) or ONO (Oxide Nitride Oxide) dielectric films. The use of high-dielectric-constant films, however, is still being studied and tested and there are problems relating to reliability.
An alternative approach is to form three-dimensional capacitors such as stacked capacitors in order to increase available surface area. Such stacked capacitors include, for example, double-stacked, fin stacked, cylindrical, spread-stacked, or box structure capacitors. Because both outer and inner surfaces of a cylindrical capacitor can be utilized as effective capacitor area, the cylindrical structure is favorable for integrated circuit memory cells such as DRAM cells among the three-dimensional stacked capacitors.
U.S. Pat. No. 5,340,765 (issued on Aug. 23, 1994) discloses a method for fabricating a capacitor structure resembling a cylindrical container. U.S. Pat. No. 5,340,763 (issued on Aug. 23, 1994) discloses more complex structures, such as the container-within-container and multiple pin structures.
Recently, new technologies have been developed for further increasing the effective surface area of DRAM cells by modifying the surface morphology of the polysilicon storage node itself. This is accomplished by engraving or controlling the nucleation and growth condition of polysilicon. A hemispherical grain (HSG) silicon layer can be deposited over a storage node to increase surface area and capacitance.
One problem associated with a capacitor having a HSG silicon layer is the formation of electrical bridges between adjacent storage nodes. Furthermore, high density DRAM devices leave only a little space for the storage nodes of a memory cell, making it difficult to employ HSG silicon in the inner surface of cylindrical capacitors and resulting in electrical bridges between opposite HSG silicon layers within the cylinder, particularly with respect to the shortest direction of cylindrical capacitors.
More specifically, in 256M DRAMs of a 170 nm design rule, a cylindrical capacitor with a HSG silicon layer has a minimum feature size of 170 nm in the shortest direction. At this time, a HSG frame conductive layer is required be at least 40 nm thick, and a HSG is about 30 nm thick. The overall thickness of the storage node having a HSG silicon layer becomes about 140 nm. Because a dielectric film is about 8 nm thick and a plate node is about 30 nm thick it is very difficult to form a dielectric film and a plate node subsequently. That is, the overall dimension of layers deposited in the cylindrical opening in the shortest direction is about 216 nm, which exceeds the design rule of 170 nm. Accordingly, it has heretofore been impossible to form a HSG silicon layer in compliance with a design rule of 170 nm.
A feature of the present invention is to provide a method for fabricating a cylindrical capacitor having a HSG silicon layer on its inner surface in a high-density integrated circuit device.
Another feature of the present invention is to form a cylindrical capacitor with a HSG silicon layer on its inner surface in order to increase the available surface area, so that a relaxed design rule in photolithographic processes can be employed by enlarging openings for storage node formation defined by the photolithographic processes by wet etching. The distance between adjacent storage nodes can be reduced to a minimum pitch of about 10 nm.
Another feature of the present invention is to form a contact plug that protrudes from the top surface of an insulating layer in which the contact plug is buried in order to reinforce the support of subsequently formed storage nodes.
According to one aspect of the present invention, a method for fabricating a DRAM cell capacitor is provided, comprising the steps of forming a moulding layer on an integrated circuit substrate, the moulding layer having an opening for a storage node, enlarging the opening by etching both sidewalls of the opening by a predetermined thickness, forming a conductive layer for the storage node in the enlarged opening and on the moulding layer, forming an insulating layer on the conductive layer to completely fill the enlarged opening, and planarizing the insulating layer and the conductive layer until the top surface of the moulding layer is exposed.
The method may further comprise the steps of forming HSG silicon nodules on the conductive layer prior to the step of forming the insulating layer, removing at least the remainder of the insulating layer in the enlarged opening subsequent to the step of planarizing the insulating layer to form a storage node, and forming a dielectric layer and a plate node to form the capacitor.
Alternatively, the method may further comprise the steps of removing the insulating layer in the enlarged opening subsequent to the step of planarizing the insulating layer and the conductive layer, forming HSG silicon nodules on the storage node, and forming a dielectric layer and a plate node to form a capacitor. In this alternate case, the method may still further comprise the step of removing the moulding layer subsequent to the step of forming the HSG silicon nodules.
In another aspect of the present invention, a method for fabricating a DRAM cell capacitor is provided, comprising the steps of forming a first insulating layer on an integrated circuit substrate, selectively etching the first insulating layer to form a contact hole, filling the contact hole with conductive material to form a contact plug, forming a moulding layer on the first insulating layer and on the contact plug, the moulding layer having an opening that exposes at least a top surface of the contact plug and a part of the first insulating layer outside the boundary of the contact plug, enlarging the opening by etching both sidewalls of the opening by a predetermined thickness, forming a conductive layer in the enlarged opening and on the moulding layer, forming HSG silicon nodules on the conductive layer, forming a second insulating layer on the HSG silicon nodules and on the conductive layer to completely fill the enlarged opening, and thereafter planarizing the second insulating layer, the HSG silicon nodules and the conductive layer until the surface of the moulding layer is exposed.
In still another aspect of the present invention, a method for fabricating a DRAM cell capacitor is provided, comprising the steps of forming a first insulating layer on an integrated circuit substrate, selectively etching the first insulating layer to form a contact hole, filling the contact hole with conductive material to form a contact plug, forming a moulding layer on the first insulating layer and on the contact plug, the moulding layer having an opening that exposes at least a top surface of the contact plug and the first insulating layer outside the boundary of tie contact plug, enlarging the opening by etching both sidewalls of the opening by a predetermined thickness, forming a conductive layer in the enlarged opening and on the moulding layer, forming a second insulating layer on the conductive layer to completely fill the enlarged opening, the second insulting layer having an etching selectivity with respect to the moulding layer, planarizing the second insulating layer and the conductive layer until the surface of the moulding layer is exposed, removing the remainder of the second insulating layer in the enlarged opening to form a storage node, and forming HSG silicon nodules on the surface of the storage node.
In still another aspect of the present invention, a method for fabricating a DRAM cell capacitor is provided, comprising the steps of forming a first insulating layer at least including a nitride layer and an oxide layer on an integrated circuit substrate, selectively etching the first insulating layer to form a contact hole, filling the contact hole with conductive material to form a contact plug, forming a moulding layer on the first insulating layer and on the contact plug, the moulding layer having an opening that exposes at least the top surface of the contact plug and the first insulating layer outside the boundary of the contact plug, enlarging the opening by etching both sidewalls of the opening by a predetermined thickness, forming a conductive layer in the enlarged opening and on the moulding layer, forming HSG silicon nodules on the conductive layer, forming a second insulating layer in the remainder of the enlarged opening and on the conductive layer, a void being formed in the enlarged opening when forming the second insulating layer, and thereafter planarizing the second insulating layer, the HSG silicon nodules and the conductive layer until the surface of the moulding layer is exposed.
In yet another aspect of the present invention, a method for fabricating a DRAM cell capacitor is provided, comprising the steps of forming a first insulating layer and a first anti-reflection layer on an integrated circuit substrate, selectively etching the first anti-reflection layer and the first insulating layer to form a contact hole, filling the contact hole with a conductive material to form a contact plug, forming a moulding layer and a second anti-reflection layer on the first anti-reflection layer and on the contact plug, etching the second anti-reflection layer and the moulding layer to form an opening that exposes at least the top surface of the contact plug and the first anti-reflection layer outside the boundary of the contact plug, removing at least the second anti-reflection layer and the first anti-reflection layer in the opening, enlarging the opening by etching both sidewalls of the opening by a predetermined thickness, forming a conductive layer in the enlarged opening and on the moulding layer, forming HSG silicon nodules on the conductive layer, forming a second insulating layer to completely fill the enlarged opening, and planarizing the second insulating layer, the HSG silicon nodules and the conductive layer until the surface of the moulding layer is exposed.
In still another aspect of the present invention, a method for fabricating a DRAM cell capacitor is provided, comprising the steps of forming a first insulating layer and a first anti-reflection layer on an integrated circuit substrate, selectively etching the first anti-reflection layer and the fire insulating layer to form a contact hole, filling the contact hole with conductive material to form a contact plug, forming a moulding layer and a second anti-reflection layer on the first anti-reflection layer and on the contact plug, etching the second anti-reflection layer and the moulding layer to form an opening that exposes at least the top surface of the contact plug and the first anti-reflection layer outside the boundary of the contact plug, removing at least the second anti-reflection layer and the first anti-reflection layer in the opening, enlarging the opening by etching both sidewalls of the opening by a predetermined thickness, forming a conductive layer in the enlarged opening and on the moulding layer, forming HSG silicon nodules on the conductive layer, forming a second insulating layer in the remainder of the enlarged opening and on the conductive layer, a void being formed in the enlarged opening when forming the second insulating layer, and thereafter planarizing the second insulating layer, the HSG silicon nodules and the conductive layer until the surface of the moulding layer is exposed.
In still another aspect of the present invention, a DRAM cell capacitor is provided, comprising an insulating layer formed on an integrated circuit substrate, a storage node formed on the insulating layer and electrically connected to the substrate via a contact plug formed in the insulating layer, the storage node being separated from adjacent storage nodes by a minimum distance of about 10 nm, HSG silicon nodules formed on the storage node, a dielectric film formed on the storage node and the HSG silicon nodules, and a plate node formed on the dielectric film.
In still another aspect of the present invention, a DRAM cell capacitor is provided, comprising an insulating layer formed on an integrated circuit substrate, the insulating layer including a contact hole, a contact plug filling the contact hole and protruding by a predetermined thickness from the top surface of the insulating layer, a storage node formed on the insulating layer and electrically connected to the contact plug, a dielectric film formed on the storage node and on the insulating layer, and a plate node formed on the dielectric film, wherein the storage node is separated from adjacent storage nodes by a minimum distance of about 10 nm.